At present, the requirement of the increasing base station data throughput causes increases in both component cost and power consumption of wireless communication units and makes related printed circuit boards and interfaces more complex, and meanwhile puts more emphasis on the requirement of signal integrity.
Thus, traditional concurrent Low-Voltage Differential Signalling (LVDS) I/O interfaces are no longer suitable for the demands on cost reduction, system reliability enhancement, integration improvement, shortening of the time to market, design complexity reduction and so on; therefore, Solid State Technology Association (JEDEC) publishes a JESD204B interface standard applicable to the universal interface of Analogue Digital Conversion (ADC)/Digital Analogue Conversion (DAC).
As the proposal of the JESD204B interface standard, how to realize the alignment of a plurality of data lanes at the receiving side and how to guarantee the determined delay of link become problems needed to be resolved urgently for the adoption of the JESD204B interface standard. However, the JESD204B interface protocol puts forward a limit that the processing delay from a data transmitting end to a data receiving data cannot exceed the length of one Local Multi Frame Clock (LMFC) (or called a local multi frame head) at most and that the delay difference between each lane cannot exceed the length of one LMFC too. However, the length of the LMFC may have a minimum of 17 bytes. Since the delay is shorter if the board level wiring is shorter, the limit of the above protocol has a high demand on hardware processing and board level wiring, so that the complexity of the design implementation is greatly increased.